CAN BUS IP CORE Documentation

Complete Reference Manual for SystemVerilog CAN BUS IP
© 2025 Maktab-e-Digital Systems Lahore
Licensed under the Apache 2.0 License

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OVERVIEW

• Project : CAN BUS IP CORE
• Target : SoC Integration
• Protocol Supported : CAN 2.0A / 2.0B
• Language : SystemVerilog

What is CAN Protocol?

CAN (Controller Area Network) is a serial communication protocol originally developed by Bosch in 1986 for use in automotive systems, but now widely used in industrial, medical, and embedded systems.

The CAN Bus IP Core is designed to transmit and receive CAN frames with full support for arbitration, error handling, bit stuffing, and CRC checking. It is intended for integration into FPGA/ASIC-based SoC designs.

Documentation Pages

This documentation is organized into specialized sections. Click on any page below to navigate:

• Home
• Installation/User Guide
• Theory of Operation
• API Reference
• Contributing

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Licensing

Licensed under the Apache License 2.0
Copyright © 2025
Maktab-e-Digital Systems Lahore